1. Field of the Invention
The present invention relates to an intermediate voltage control circuit within integrated circuit chips, and more particularly, to an intermediate voltage control for applying intermediate voltage to a signal line such as digit line connected to a memory cell of a semiconductor memory circuit or a data line connected to a sense amplifier.
2. Description of Related Art
An intermediate voltage control circuit is used to supply an intermediate voltage to a signal line while data is not accessed. More particularly, an intermediate voltage control circuit employs an n-channel transistor in its charging path and a p-channel transistor in its discharging path, respectively.
FIG. 5 shows a circuit diagram describing a configuration of an intermediate potential generator circuit disclosed in Japanese Kokai No. 8-171432. The intermediate generator circuit shown in FIG. 5 is configured by reference potential generating circuit 550 and output circuit 552. The reference potential generating circuit generates (xc2xd) Vcc+Vtn as a reference potential Vref1 and (xc2xd) Vccxe2x88x92|Vtp| as a reference potential Vref2, respectively. The output circuit includes an n-channel MOS transistor 521 and a p-channel MOS transistor 522. In the n-channel MOS transistor 521, a drain electrode is connected to a power node 500 and a source electrode is connected to an output node 54. In the p-channel MOS transistor 522, the source electrode is connected to the output node 54 and the drain electrode is connected to a ground node 600. Those transistors 521 and 522 are connected to each other serially between the power node 500 and the ground node 600. The voltage of the output node is fed back to the gate electrodes of the p-channel MOS transistor 501 and the n-channel MOS transistor 504 in the reference voltage generating circuit, respectively.
Vref1 is sent to the gate electrode of the n-channel MOS transistor 521 of the output circuit and Vref2 is sent to the gate electrode of the p-channel MOS transistor 522 of the output circuit. Both of the transistors 521 and 522 are slightly conductive.
In case the voltage of the output node 54 drops, the conductive resistance of the n-channel MOS transistor 521 is reduced, whereby a current flows from the power node 500 to the output node 54 via the transistor 521. The voltage of the output node thus rises. At the same time, because this output node voltage is fed back to the gate electrode of the p-channel MOS transistor 501 in the reference voltage generating circuit, the conductive resistance of the transistor 501 is reduced, whereby a current flows to the node N1. The potential of the gate electrode of the transistor 521 thus rises and the voltage of the output node 54 returns immediately to its initial intermediate potential (xc2xd) Vcc.
On the other hand, in case the voltage of the output node 54 rises, the conductive resistances of the p-channel MOS transistor 522 and the n-channel MOS transistor 504 are reduced in the same way, whereby the voltage of the output node 54 returns immediately to its initial intermediate potential.
The conventional technique drives the potential of the output node 54 to an intermediate potential in this manner.
However, in the intermediate potential generator circuit shown in FIG. 5, because the n-channel MOS transistor 521 and the p-channel MOS transistor 522 connected to each other serially in the output means 52 are slightly conductive, a current continues to flow from the power node 500 to the ground node 600. Therefore, wasted power consumption is ongoing in this region.
An object of the present invention is to provide an intermediate voltage control circuit, which reduces power consumption.
An another object of the present invention is to provide an intermediate voltage control circuit, which outputs stable intermediate voltage.
An intermediate voltage control circuit according to the present invention includes: a monitoring circuit that determines whether the voltage level of a signal line connected to an output node is higher or lower than a predetermined target voltage so as to generate a determination signal; a first n-channel transistor in which the drain is connected to a power node and the source is connected to the output node; a second p-channel transistor in which the drain is connected to a ground node and the source is connected to the output node; and a control circuit that generates a first control signal to be sent to the gate of the first n-channel transistor and a second control signal to be sent to the gate of the second p-channel transistor based on the determination signal received from the monitoring circuit and an enable signal received from an external input node. The control circuit controls the on/off operation of the first and second transistors as follows: in case the enable signal is active and the determination signal received from the monitoring circuit denotes that the voltage of the signal line is high, the control circuit sets both of the first and second control signals to low and in case the determination signal received from the monitoring circuit denotes that the voltage of the signal line is low, the control circuit sets both of the first and second control signals to high so as to turn on/off the first and second transistors, and in case the enable signal is inactive, the control circuit sets the first control signal to low and the second control signal to the high respectively so as to turn off both of the first and second transistors.
The above-described intermediate voltage control circuit is suitable for a semiconductor memory device which incorporates its own intermediate voltage control circuit.
These and other objects of the present invention will be apparent to those of skill in the art from the appended claims when read in light of the following specification and accompanying figures.